1. Field of the Invention
The invention relates generally to a method of forming a source contact of a NAND flash memory and, more particularly, to a method of forming a source contact of a NAND flash memory, wherein source lines are formed simultaneously with the gate formation process, whereby there is no reduction in the Depth of Focus (DOF) even if the size of select transistors is shrunk.
2. Discussion of Related Art
As the line width of flash memory devices has become smaller, minute and the depth of contact holes has increased, electrical interconnections between upper and lower lines in the contact hole has become more difficult.
In general, in the flash memory device, an open area exists between the select transistors including a source select transistor (SST) and a drain select transistor (DST) in order to secure the space with the source lines to be formed after the formation of the gate.
The select transistor is substantially an important factor to decide the die size of the flash memory device. To reduce the cell size, it is necessary to reduce the select transistor size.
However, since a wide-open area exists between the select transistors as described above the DOF is reduced if the select transistors are reduced in size. Accordingly, a problem arises because it is very difficult to reduce the size of the select transistors to a specific size or less.
In other words, in the case where a minute metal line is to be formed by a photolithography process (as is generally used in the metal line), the step by the topology of the interlayer insulating layer causes a defocus phenomenon in the photolithography process for forming the metal wiring or the contact hole because an optical system has a relatively shallow DOF. As a result, there is a problem in that pattern failure is generated.